In general, an image sensor is a semiconductor device for converting optical images into electric signals, and is classified into a charge coupled device (CCD) or a CMOS image sensor.
A CCD has a plurality of photodiodes (PDs), which are arranged in the form of a matrix in order to convert optical signals into electric signals. CCDs also include a plurality of vertical charge coupled devices (VCCDs) provided between photodiodes vertically arranged in the matrix. The VCCDs transmit electric charges in the vertical direction when the electric charges are generated from each photodiode. Additionally, CCDs have a plurality of horizontal charge coupled devices (HCCDs) for transmitting the electric charges that have been transmitted from the VCCDs in the horizontal direction; and a sense amplifier for outputting electric signals by sensing the electric charges being transmitted in the horizontal direction.
However, a CCD image sensor has various disadvantages, such as a complicated drive mode and high power consumption. Also, the CCD requires multi-step photo processes, so the manufacturing process is complicated.
In addition, it is difficult to integrate a controller, a signal processor, and an analog/digital converter (A/D converter) onto a single chip of the CCD. This leads to the CCD being unsuitable for compact-size products.
Recently, the CMOS image sensor has been spotlighted as a next-generation image sensor capable of solving the problems of the CCD.
The CMOS image sensor is a device employing a switching mode to sequentially detect an output of each unit pixel by means of MOS transistors using peripheral devices such as a controller and a signal processor. The MOS transistors are formed on a semiconductor substrate corresponding to each of the unit pixels through a CMOS technology.
That is, the CMOS sensor includes a photodiode PD and a MOS transistor in each unit pixel, and sequentially detects the electric signals of each unit pixel through the MOS transistor in a switching mode, so as to realize an image.
Since the CMOS image sensor makes use of the CMOS technology, the CMOS image sensor has advantages such as low power consumption and a simple manufacturing process with relatively fewer photo processing steps.
In addition, the CMOS image sensor allows the product to have a compact size because the controller, the signal processor, and the A/D converter can be integrated onto a single chip.
Accordingly, the CMOS image sensor has been extensively used in various applications, such as digital still cameras and digital video cameras.
The CMOS image sensors are classified into 3T, 4T and 5T-type CMOS image sensors according to the number of transistors formed in each unit pixel. The 3T-type includes one photodiode and three transistors, and the 4T-type includes one photodiode and four transistors.
The layout for a unit pixel of the 4T-type CMOS image sensor will now be described.
FIG. 1 is an equivalent circuit of a 4T-type CMOS image sensor according to a related art, and FIG. 2 is a layout showing a unit pixel of the 4T-type CMOS image sensor according to the related art.
As shown in FIG. 1, a unit pixel 100 of the CMOS image sensor includes a photodiode 10 serving as a photoelectric converting part and four transistors.
The four transistors are transfer, reset drive and selection transistors 20, 30, 40 and 50, respectively. Further, a load transistor 60 is electrically connected to an output terminal OUT of each unit pixel 100.
Reference character FD denotes a floating diffusion area, and reference characters Tx, Rx, and Sx denote gate voltages of the transfer, reset, and selection transistors 20, 30, and 50, respectively.
As shown in FIG. 2, the unit pixel of the 4T-type CMOS image sensor has an active area defined thereon. An isolation layer is formed on a predetermined area of the unit pixel, but not on the active area. One photodiode PD is formed on a wider region of the active area, and gate electrodes 23, 33, 43 and 53 of four transistors are formed overlapping the remaining regions of the active area.
The first gate electrode 23 corresponds to the transfer transistor 20, the second gate electrode 33 incorporates with corresponds to the reset transistor 30, the third gate electrode 43 corresponds to the drive transistor 40, and the fourth gate electrode 53 corresponds to the select transistor 50.
Dopants are implanted into the active area of each transistor except for below lower portions of the gate electrodes 23, 33, 43 and 53. This causes the formation of source/drain (S/D) areas of the transistors.
FIGS. 3A to 3C are sectional views taken along line I-I′ of FIG. 2 and illustrate a manufacturing process of a CMOS image sensor according to the related art.
Referring to FIG. 3A, a low density P type epitaxial layer 62 is formed on a high density P type semiconductor substrate 61 through an epitaxial process.
Subsequently, an active area and an isolation area are defined on the semiconductor substrate 61, and an isolation layer 63 is formed in the isolation area through an STI process.
In addition, an insulating layer and a conductive layer (for example, a high-density multi-crystalline silicon layer) are sequentially deposited on the entire surface of the epitaxial layer 62 formed with the isolation layer 63. Then, the conductive layer and the insulating layer are selectively removed, thereby forming a gate electrode 65 and a gate insulating layer 64.
Next, referring to FIG. 3B, a first photoresist film is coated on the entire surface of the semiconductor substrate 61 and patterned through an exposure and development process in such a manner that blue, green and red photodiode areas are exposed.
Then, low-density N type dopants are implanted onto the epitaxial layer 62 by using the patterned first photoresist film as a mask, thereby forming a low-density N type diffusion area 67 that serves as blue, green and red photodiode areas.
Subsequently, the first photoresist film is completely removed, an insulating layer is deposited on the entire surface of the semiconductor substrate 61, and an etchback process is performed to form spacers 68 at both sides of the gate electrode 65.
Next, a second photoresist film is coated on the entire surface of the semiconductor substrate 61 and patterned through an exposure and development process, such that the photodiode area is covered and the source/drain area of each transistor is exposed.
Then, high-density n type dopants are implanted onto the exposed source/drain area by using the patterned second photoresist film as a mask, thereby forming an n type diffusion area (floating diffusion area) 70.
After that, referring to FIG. 3D, the second photoresist film is removed, and a third photoresist film is coated on the entire surface of the semiconductor substrate 61. An exposure and development process is performed with respect to the third photoresist film, so that it is patterned to expose each photodiode area.
Then, p type dopants are implanted onto the photodiode area having the n type diffusion area 67 by using the patterned third photoresist film as a mask, thereby forming a p type diffusion area 72 on the surface of the semiconductor substrate. Then, the third photoresist film is removed, and a heat-treatment process is performed with respect to the semiconductor substrate 61, thereby expanding each impurity diffusion area.
During operation, electrons are generated in the photodiode area by the incident light. The transfer transistor is turned on to transfer the generated electrons from the photodiode area, which is the N type diffusion area 67, to the N type diffusion area 70 for temporary storage.
However, punchthrough (see reference numeral 76) between the N type diffusion area 70 and the low-density N type diffusion area 67 of the transfer transistor may be caused by the expansion of a depletion area 74 of the N type diffusion area 67 formed in the photodiode area, thereby degrading the characteristic of the CMOS image sensor.